Performance Modelling of Intel’s Hardware Transactional Memory Implementation

Transactional Memory (TM) is a recent alternative to traditional lock based synchronization mechanisms for parallel programming. This report analyses the state of the art in the area of performance modelling for transactional memory systems, as well as for concurrency control mechanisms for database management systems. My analysis of existing literature in these areas highlights the existence of a relevant gap, which I aim to fill with my thesis work: the lack of performance models for hardware-based implementations of TM, also known as Hardware Transactional Memory (HTM). More in detail, my dissertation will be aimed at building simulative and analytical models capable of capturing the performance dynamics of Intel’s implementation of HTM. In addition to defining the goals of my dissertation, this document also discusses initial ideas and preliminary results achieved so far.